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Silicon Motion targets PCIe 7.0 SSDs for 2027
Silicon Motion has defined its PCIe 7.0 SSD controller architecture, with first samples due in the second half of 2027.
Image: iXBT
Silicon Motion has started developing an enterprise SSD controller with PCIe 7.0 support, with the first samples expected in the second half of 2027. According to Alex Chou, the head of the company’s enterprise storage business, the basic architecture for the new Gen7 controller has already been defined.
Before that arrives, the company still has to finish its previous generation. Its PCIe 6.0 SSD controller is already at the FPGA emulation stage, and the first silicon samples are expected in the second half of 2026.
Modern SSD controllers require more than just a faster interface. They also depend on coordinated development of firmware, error correction, encryption, virtualization, wear leveling, and latency control.
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The PCIe 7.0 specification was approved by PCI-SIG on June 11, 2025. The new standard doubles data transfer speed over PCIe 6.0, reaching 128 GB/s per lane, while retaining PAM4 signaling and FLIT mode. For x16 connections, that translates to up to 512 GB/s in both directions. For the x4 link commonly used by SSDs, the theoretical ceiling is about 64 GB/s one way.
Actual SSD performance will still depend on the controller, NAND memory, channel count, power use, and cooling.
One of Silicon Motion’s main targets for these next-generation SSDs is AI infrastructure. The company links the effort to Nvidia Storage Next, an initiative aimed at reducing latency between storage and GPUs. In these workloads, raw sequential throughput matters, but so does consistent performance when multiple GPUs, virtual machines, and users hit storage at the same time.
Silicon Motion says it expects gains in workloads with large volumes of parallel operations and sees tens of millions of IOPS as achievable. The company considers the previously discussed 100 million to 200 million IOPS range unrealistic in the near term, while about 50 million IOPS looks more attainable. It also plans to improve LDPC error-correction algorithms for future NAND generations.
For now, PCIe 7.0 remains a server and AI-infrastructure story rather than one for home PCs. Mass adoption will require compatible platforms, shipping PCIe 6.0 SSDs, and NAND capable of taking advantage of the new interface.
Enterprise Editor
Marcus follows the money. He covers enterprise software, cloud architecture, and the tectonic shifts in Big Tech strategy. He translates dense earnings calls and complex M&A activity into actionable insights about where the industry is actually heading. If a tech giant makes a silent pivot, Marcus is usually the first to notice.
via iXBT
